A Novel Power Delay Optimized 32-bit Parallel Prefix Adder For High Speed Computing
نویسندگان
چکیده
Parallel Prefix addition is a technique for improving the speed of binary addition. Due to continuing integrating intensity and the growing needs of portable devices, low-power and high-performance designs are of prime importance. The classical parallel prefix adder structures presented in the literature over the years optimize for logic depth, area, fan-out and interconnect count of logic circuits. In this paper, a new architecture for performing 32-bit Parallel Prefix addition is proposed. The proposed 32-bit prefix adder is compared with several classical adders of same bit width in terms of power, delay and number of computational nodes. The results reveal that the proposed 32-bit Parallel Prefix adder has the least power delay product when compared with its peer existing Prefix adder structures. Tanner EDA tool was used for simulating the adder designs in the TSMC 180 nm and TSMC 130 nm technologies.
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